Devices that capture and display sequences of address, data, and status information, etc.,, are known as logic state analyzers. See, for instance, the August 1975, and February 1978, issues of the Hewlett-Packard Journal.
Heretofore, logic state analyzers have not been able to capture collections of data occurring separately in time and subsequently treat the combined collection as a single parallel entity, as if it had actually occurred as a single entity and had been captured all at once. Such a capability would be highly desirable when working with microprocessors incorporating time-multiplexed busses, for example. In such instances the same lines carry electrical signals whose meanings, such as "address", "data" or "status" are dependent upon previous events (i.e., the "state of the system" under test). Often, the "state of the system" is indicated by other signals that may be thought of as "qualifiers" indicating that: an address is present; a memory cycle is a read or a write; an instruction fetch is underway; a DMA memory cycle is in progress; or that an interrupt request is in effect or has been granted. Once the "qualifiers" indicate the "state of the system" it is often the case that a particular clock signal or other signal may be used to strobe data of interest occurring during that particular "state of the system". It is frequently the case that time sequences of such "states of the system" are most conveniently thought of as homogeneous entities. For example, a memory cycle can be conceived of as an address and something either written to or read from that address. No further insight is provided to the logical flow of operations concerning memory by enforcing a time separation between the two for logic state analysis purposes merely because it is expedient to do so in the particular hardware implementation at hand. Indeed, exactly the opposite is true, as such a division amounts to an undesirable overhead operation that consumes extra space in the formatted display and that requires extra user attention to interpret.
According to a preferred embodiment of the invention a logic state analyzer is provided with a multiplicity of clock monitoring circuits whose outputs are then each independently qualified according to the "qualifiers" mentioned above. Each such qualified clock signal representing a selected "state of the system". Separate data capture circuits correspond to each of the qualified clock signals. As each "state of the system" that is of interest occurs the associated data capture circuit captures the relevant data. Such data may occur either at separate times upon the same bus or at the same time at disparate locations. A user selectable qualified combination, or "state of the system", occurring not earlier than any other "state of the system" also of interest is designated as a master transfer signal. That signal causes simultaneous transfer of the current contents of each of the data capture circuits into a single merged parallel representation that is then stored in a memory for subsequent formatted display to the user.